One of the common elements required in electrical circuit devices is the simple pullup (or pulldown device) from an active device to one of the power supply buses. The pullup is simple if used to construct a circuit using discrete components in that all that is required is selecting a resistor of the desired resistance and tolerance, connecting it between an active device, such as an open collector transistor, and V.sub.CC and the transistor's output would be pulled up to V.sub.CC once the transistor is forward biased. With the advent of the integrated circuit (IC) however, fabricating a resistance onto a wafer substrate, such as silicon or gallium arsenide, takes special consideration particularly when resistivity and tolerances play an important part in circuit operation.
For example, as SRAMs have evolved from the small 4Kb memory arrays to more densely packed array sizes, tolerances of pullup resistances (or pullup loads) had to be tightly controlled. In order to minimize standby current many fabrication processes adopted using an active device as the pullup. In CMOS fabrication it is common to see a PMOS transistor acting an active load device, by providing a current path between a memory cell access transistor and the power supply bus. In this manner the PMOS transistor could be gated on only when the desired line was to be pulled to V.sub.CC and turned off otherwise, thereby virtually eliminating leakage current and minimizing standby current for the SRAM device as a whole.
Ongoing efforts to improve active loads has brought about the development of thin film transistors (TFTs) in attempts to provide low leakage current as well as high noise immunity. In a article entitled "A High-Performance Stacked-CMOS SRAM Cell by Solid Phase Growth Technique", pp. 21-22, 1990 Symposium on VLSI Technology, by Y. Uemoto et. al., such a TFT device is disclosed. This article presents a high performance stacked-CMOS SRAM cell with improved polysilicon p-ch TFT load-characteristics that is attained by enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a solid phase growth (SPG) technique. Basically the grain size of the polysilicon film is controlled by the deposition temperature and the surface roughness is controlled by using ion-implantation for forming the gate for the p-ch TFT instead of by thermal diffusion.
The present invention introduces a TFT having an epitaxially regrown silicon channel region by using a method which provides a solid phase epitaxial regrowth of silicon in a thin film of amorphous silicon for the TFT by using the silicon substrate as a seed.